Abstract:

The evolution of modern electronics toward compact, high-performance, and energy-efficient systems has intensified the need for low-power Very-Large-Scale Integration (VLSI) design, particularly for next-generation devices such as wearable electronics, Internet of Things (IoT) nodes, biomedical implants, and mobile platforms. Low-power VLSI design addresses the challenges of reducing power consumption without compromising performance, area, and reliability. As device scaling approaches its physical limits, power dissipation due to leakage currents, dynamic switching, and short-circuit paths becomes a dominant concern, necessitating novel design methodologies and architectures. Techniques such as voltage scaling, clock gating, power gating, multi-threshold CMOS (MTCMOS), and dynamic voltage and frequency scaling (DVFS) are extensively researched and deployed to achieve optimal trade-offs. Moreover, emerging technologies like FinFETs, Tunnel FETs, and 3D integration are further enabling innovations in low-power architectures. By integrating advanced circuit-level strategies with algorithmic and architectural optimizations, low-power VLSI design is becoming pivotal in supporting the energy constraints and performance demands of future electronic systems, ensuring sustainable and scalable growth in the semiconductor industry.